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This paper presents a novel system architecture to suppress in-band artifacts (IBAs) generated from out-of-band (OOB) interferers, including reciprocal mixing by the local oscillator's (LO) spurs and phase noise (PN), third-order intermodulation (IM3) artifacts, and harmonic down-conversion (HDC) artifacts. Theory and design procedure are explained, and measurement results from a prototype taped out in 45nm RF SOI process are presented. The receiver was designed for the frequency range of 1.2-2.4GHz and achieved a noise figure (NF) of 3.1-6.2dB, blocker -1dB compression point (B1dB) of -10.3Bm, and OOB third-order input-referred intercept point (IIP3) of 9.3dBm on average, before artifact suppression. Measurements were performed on 16-quadrature amplitude modulated (16QAM) signals with modulated and unmodulated OOB interferers to show artifact suppression for various kinds of IBA. For each IBA, artifact suppression performance was assessed across frequency and interferer power. Interference tolerance improvement of up to 38dB was achieved. Additionally, reconstruction of the artifacts for the cases of spur and HDC was demonstrated, showing simultaneous recovery of two signals, providing a form of carrier aggregation.more » « less
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Castaneda, Oscar; Boynton, Zachariah; Mirfarshbafan, Seyed Hadi; Huang, Shimin; Ye, Jamie C.; Molnar, Alyosha; Studer, Christoph (, IEEE 47th European Solid State Circuits Conference (ESSCIRC))All-digital millimeter-wave (mmWave) massive multi-user multiple-input multiple-output (MU-MIMO) receivers enable extreme data rates but require high power consumption. In order to reduce power consumption, this paper presents the first resolution-adaptive all-digital receiver ASIC that is able to adjust the resolution of the data-converters and baseband-processing engine to the instantaneous communication scenario. The scalable 32-antenna, 65 nm CMOS receiver occupies a total area of 8 mm 2 and integrates analog-to-digital converters (ADCs) with programmable gain and resolution, beamspace channel estimation, and a resolution-adaptive processing-in-memory spatial equalizer. With 6-bit ADC samples and a 4-bit spatial equalizer, our ASIC achieves a throughput of 9.98 Gb/s while being at least 2× more energy-efficient than state-of-the-art designs.more » « less
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